Smart Dust will require both evolutionary and revolutionary advances in miniaturization, integration, and energy management. These advances will be facilitated by the progress in micro electromechanical systems (MEMS), which allows us to build small sensors, communication components, and power supplies, and microelectronics, which provides increasing amounts of functionality in smaller areas and with lower energy consumption. The power system may consist of a thick film battery and/or a solar cell with a charge integrating capacitor for periods of darkness. A variety of sensors, including light, temperature, vibration, magnetic field, acoustic, and wind shear, can be integrated on the mote depending upon the mission. An integrated circuit will provide sensor signal processing, communication, control, data storage, and energy management.
Because of the small size of the mote, energy management
is a key component of the design. Current battery and capacitor technology
can store approximately 1J/mm3 and 10mJ/mm3, respectively,
while solar cells can provide 1J/day/mm2 in sunlight and 1-100mJ/day/mm2
indoors. Energy consumption must therefore be minimized in every
part of the system.
The mote controller will provide back-end communications
processing, sensor sampling control and signal processing, data storage,
and energy management. In addition, because of the difficulties imposed
by the size of the mote the processor needs to be reprogrammable over the
communications channel. We are therefore designing new low energy
processors that meet the needs of the mote. One architecture is a
somewhat traditional controller/datapath organization, but a new architecture
is also being designed that provides substantial energy savings through
a better matching between the architecture and the application space.
Since the mote is very dependent on the environment, yet even checking
the environment for signals is expensive energy-wise, we utilize a reactive
architecture that employs reconfigurable datapath components that are set
up to execute an operation only when required by timers that control the
frequency of the polling.
Our new controller architecture shows promise of being substantially superior for our application than competitive microcontroller architectures. One of the most efficient microcontrollers available is the CoolRisc 81 core that uses 22pJ/instruction, as compared to the StrongARM SA1100 that consumes ~1nJ/instruction. To perform a typical sequence of operations, preliminary simulations predict that our new architecture will use 4.8pJ, while the CoolRisc 81 would require 136pJ.
These demonstrations indicate that we are successfully exploring the limits of complex system miniaturization and energy efficiency, while producing a device that will change the way we think about gathering data from the environment.