An Integrated Circuit for the in situ Characterization of CMOS Post-Process Micromachining
Motivation for CMOS Micromachining
CMOS Micromachining Applications
CMOS Post-Process Micromachining
The Problem
Basic Pit Test Structure
Pit Variations
Layout
Photomicrograph after Etching
Pit Cross-sections
Architecture
in situ Readout System
Demultiplexed Waveforms
Etch Rate vs. Pit Size and Layers
Etch Rate vs. Slope and Layers
Conclusion
Rising Data Discussion
Pointer Circuit
Email: warneke@eecs.berkeley.edu
Home Page: http://www.eecs.berkeley.edu/~warneke