Verilog Tips

Verilog Devlopment

If you run Comparescan on a database that is already open in Signalscan/SimControl, it runs much slower (~2 orders)
Verilog uses square brackets for busses, but Cadence uses angle brackets, so Verilog In adds little 'tran' devices that all the net to be renamed. However, there is no hspice view, so it can't be netlisted. I deleted them and renamed the nets.
When using SimVision and Signalscan, $shm_probe on an entire module loads up much quicker than doing each individual signal. I think what signals are actually plotted is stored elsewhere, so I should plot the whole module then delete the signals I don't want to watch. debug.vxl can be edited to fix this after a setup has been saved in SimVision

output ports may also need a reg definition
inout ports can't have a reg declaration in the module
inputs and inouts can have a wire declaration
continuous assignments (assign outside a procedure (initial or always blocks)) are used for nets and wires
procedural assignments (inside initial or always blocks) are for reg types

blocking delays aren't allowed (#n)
signed variables are not allowed
must be consistent with non-blocking and blocking procedural assignments for each variable.
"All asynchronous conditions must be tested in an "if" statement"

I put them all in an if, but it complained about not being a simple reset condition
I then removed all but one, and it wanted an 'else' condition
ended up having to remove the posedge in the always

Warning: Only simple variables are checked in the sensitivity list.
Warning: Variable ' ' is being read in routine xxx but does not occur in the timing control of the block which begins there.
Warning: Variable ' ' is driven in more than one process or block
Warning: Clock signal is not in the sensitivity list
Every output needs to be specified in every case of a state machine or else a latch will be inferred
the reset condition of a flip-flop always block can only be a simple identifier or its negation
Flip-flop presets are active low
if the flip-flop set is first followed by the clear using "else if", logic will be added to enforce this. For the other way around no extra logic included.
Sometimes Design Analyzer will use the Q output of a DFF and follow it with a TBUF, but other times it will use QZ and follow it with a TINV. It isn't even consistent on a single bus, so I am not sure how to convince it to use TINV all the time. I tried setting the default FF to DFFNX2 and explicitly including an inversion in the behavioral model. Setting for timing optimizations sometimes made a difference.
Design Compiler destroys the vector nets within cells and changes their names, so you can't really probe them easily anymore. I made some shell scripts (rmbs and loop) to try to fix things, but the damage is too severe.

when import verilog, list VBULK as a VDD node; otherwise it gives and error that it is shorted to VDD
after streaming in the layout from SE, select all labels on TXT layers then group them into a new cell. Use "create pins from labels" on this cell. I specified MET? drawing layers to create shape pins, but Jason suggested using MET? pin layers.
VerilogIn - defaults are stored in ~/.ihdl*
the reference library order list needs to be specified because of teh VIA cells

Use Virtuoso XL from the beginning to create the layout. Place the "layout" view at the start of the stop view, or it will descend into the P&R cell.
turned off the incremental update option

envSetVal("layoutXL" "viewList" 'string "layout schematic netlist symbol compacted symbolic")
envGetVal("layoutXL" "viewList" 'string)
envGetVal("layoutXL" "stopList" 'string)

name = "lxStopList", value = "layout"
name = "lxViewList", value = "layout schematic netlist symbol compacted symbolic"

Export to router - set Conductor depth and keepout depth to 3 (limited by the pads) to help reduce the database size. This did speed up the translation.
Autoroute -> Power Route -> Route with OutputPads selected, then choosing the power nets, routed the I/O ring even around corners and past the paddiode cells!
Global routing didn't seem to do much. It only bundled two wires -- the sensor power lines
"Pin to trunk" power routing did not work no matter what combination of selecting and specifying components and nets
pre-routing busses didn't do anything, even after I bundled up all the memory busses
Detail routing: even when specifying 5 routing passes, it halted after one for no apparent reason. It also only routed the inst bus. I realized that that bus was still selected from bundling the nets. When I deselected all nets, it started routing fine. It still wasn't able to route all the nets, and there were 15 conflicts. I quit, went back to Virtuoso and moved the blocks around to provide some more routing space, then went back through the route process.
2nd route: still couldn't do a "pin to trunk" preroute; skipped all the global routes. Detail routing couldn't get three routes and left 9 conflicts. The reason for these problems were:

I had M1 spacing set to 1um instead of 0.6um, which didn't allow dropping into the standard cells.
power nets were set to be 10um wide, which wrecked havoc with the standard cells and the extension on such a wide path bled over

I noticed that most of the fat power wires still only had one tiny contact. Supposedly CCAR should array them automatically, but maybe since these are via_images instead of via_array_templates, it isn't doing such a good job. I need to experiment with using symbol vias instead of these layout view vias. I did finally see some wires with multiple vias, so I realized that one problem is that the route.rules file specifies a via spacing of 1.2, instead of 1.0, which could be preventing more from fitting.
There was one net left unconnected (it looks connected) and one unclear conflict. I decided to wait to fix these in Virtuoso
Post-routes (filter, remove notches) didn't seem to do much. End cap had some messages, but I'm not sure what happened. It did say that min area rule only works with via_array_templates
it found a lot of antenna errors, but I think I'll wait for the normal checker
notches:

set same_net_check on
route 3
this increased my conflicts back up to 115. I just used the session file from before the notch fix instead.

in Virtuoso I went around fixing up the power nets, noteably adding more vias; this is one of the big things that still needs worked on in the CCAR setup, besides sizing of the wires. I set up regions around the WLpulse logic where the power nets were to be only 3um, but it still seemed to make them quite large; causing problems.
rules.rul contains most of the rules that I set up for CCAR. *.did files contains all the actions. I might make up a .do file.