Sometimes synopsys gives "assign" statement in its output codes, for example,
when it need to convert one data type from wire to reg. 

Those assign statement can cause problem in both VerilogIn and Silicon Ensemble.  NSC has codes to remove those lines, however, it results in connections broken, and you'll have to fix that somehow.

To tell synopsys NOT using assign statement, do the following in dc_shell (command window in design_analyzer):
1. verilogout_no_tri=true
2. set_fix_multiple_port_nets -all -buffer_constants

use man to see manuals of those variables.