Creating a Standard Cell Library

Documentation

• in the DSMSE5.3 set of documentation: Envisia Abstract Generator User Guide
• appendix D has Library Design Guidelines
• General guidelines
• all objects belonging to the cell must be inside the cell boundary
• minimizing cell size does not necessarily minimize die size; need to consider routing
• all cell widths should be a multiple of the pin grid
• placement should be on snap grid so edges of cells on grid
• small cells can have pin placement to allow Z-shape M2 routes
• place pins on grid wherever possible
• pin rectangle centered at grid intersection
• pin rectangle encloses grid intersection on all four sides by half the min. metal width
• special pins - routed by special net router and have different shapes
• don't have to be on grid, but must not interfere with adjacent grid lines
• define in DEF file
• avoid power and ground pins on M2
• power and ground pins must have a shape property defined, with value set to either feedthru or abutment
• all power and ground pins must have the same Y offset from the cell origin so followpins command works
• maximize pin accessbility
• declare complete geometry of pin as a pin
• avoid geometries on same layer close to pin, blocking it
• don't block access through vias with geometry on other layers
• stagger pins in X and Y
• do not add extra pieces of metal to provide extra connection points
• Determining Routing Grid Pitch
• define min pitch for each layer in preferred direction track -- should be at least line-to-via distance: half metal width + metal spacing + half via (including overlap)
• increase spacing to allow diagonally-adjacent vias
• align tracks on layers with same preferred direction as much as possible
• Blockages
• xlite does not seem to use a single blockage, just the layer geometry
• appendix B has sample flows

Creating the layout views

• Copy the xliteMS_core library then delete all the extraneous cells that you don't plan to convert.
• For each layout view, delete all the normal layers and draw the new layout.  Draw a Pin requirements:
• place them on a grid.  The xliteMS_core library uses a 0.9µm grid, while I used a 0.5µm grid.
• MET1TXT drawing layer for labels
• MET1PRT drawing
• MET1 pin
• under connectivity you can specify I/O type and access direction
• Open the verilog view of each cell, go to Edit-properties, then find the line that says "portOrder." If you see such a line, left click in the corresponding box and hit the delete button at the top of the box, not on the keyboard.

Creating the abstract views

• Abstract views are used by SPR tools to increase performance by removing extraneous information.
• Stream out the cells with no layer map file.  You can do the entire library at once by leaving the cell name field blank.  You probably want to set the conversion option to "merge polygons" and set case to "preserve".
• Copy a tech.dpux file into your working directory.  Mine is in ~cadence/national/cmosx/SEfiles/tech.dpux.  See the reference material below for more information.
• Launch the Envisia Abstract Generator with "abstract -tech <path to tech dir> &"
• this program crashes a lot.  Just kill it and restart.  You usually won't lose your work other than in the Technology editor.
• Go to File->Technology to edit the technology file for your needs.  At the very least, the library name will need to be changed.  Set this to an empty temporary library that you have created.  You may also need to edit the layers.  Layers that aren't used for routing, like NWELL, don't need to be included.  Save the tech file and close the window.  Don't hit the Help menu -- it might freeze.
• Go to File->Library to load up the library you specified in the tech file setup.  When I used my copy of the whole library that had abstract views for every cell, it choked and I had to kill the abstract generator process.  This is the reason for the temporary library.
• Go to File->Import->Stream... and enter your GDSII file that you streamed out above.  After importing the cells, it will list the number of cells it read in to each bin (by default "core").
• You may want to enter logical data from a Verilog view or a timing file.  However, we haven't attempted this yet.
• You can view the layout as a check by going to Cells->Edit->Layout
• Run each of the abstract generation steps in sequence, fixing problems that might show up: pins, extract, abstract, verify
• Pins
• pins are lost in the GDSII translation, so you can specify a mapping from text on a layer to pins on a layer
• If you have uniform output names (such as 'Y' and 'Q'), you can just list them so that they automatically have the output property
• If you prBoundary (where you want to abut cells) doesn't exactly correspond to 0 and 0, you can provide on offset in the boundary tab
• Extract - pretty much used defaults
• Abstract - pretty much used defaults
• Verify
• Check tab - can't check terminals unless you imported logical data
• Target tab - actually runs SE and tries routing the cell(s) including adding mirrored versions
• Cells->Report to read the results.  When I ran it, the text was white on white, so I had to highlight it in order to read it.
• Cells -> Cell Properties can be used to specify the symmetry of the cells.  By default there should be symmetry about X and Y, meaning that the cells can be flipped and tiled about those axes.  Pad cells should have X Y R90 symmetry