Tips on running Design Analyzer on BWRC account
11/21/01
1. Acquire an BWRC account by contacting Brian Richards
(richards@eecs.berkeley.edu).
2. Copy necessary library files from BSAC to BWRC account,
for example:
If you want to use Mix-signal library, you’ll need the
following files:
xliteMS_core.add_synop_scr xliteMS_core.lib
xliteMS_core.sdb
xliteMS_core.db xliteMS_core.rpt
xliteMS_core.slib
All above files can be found under:
/designPackages/cmos8/R4.0/release/libraries/mixed_signal/xliteMS_core_07/combined/synopsys_1999.05/libraries
If you want to use Std-digital library, io cells, or memories, find corresponding files under:
/designPackages/cmos8/R4.0/release/libraries
3. Log on to one of BWRC machine (say, sunu2-2) and type design_analyzer& to start the tool.
4. When first using synopsys, setup->defaults, fill in the forms. For example:
search
path: .
/tools/synopsys2000.05/libraries/syn ~/synopsys/mylib
~/synopsys/nsc_lib/mixed_signal ~/synopsys/nsc_lib/std_digital
link
library: * xlite_core.db
target
library: xlite_core.db
symbol
library: xlite_core.db
schematic
options: -size infinite
A file called synopsys_dc.setup is generated in home direcotry. Later when you want to permanently change default of setup, it seems you have to edit this file MANUALLY.
5. Read in synthesizable Verilog file using File->Read. If you see a “1” at the end of “verilog” window, it means import is successful.
-Find your top level module among the modules showed up.
-Double click to descend into details and see lower level modules. If it’s the first time you descend into a module, you’ll see symbol view first, then double click again to see details.
6. Specify Attributes for the chip. There are two ways: first, using the Attributes menu; second, write script through command window. Specify as many attribute as applied.
-go to a detail view of a module and click on “chip” icon on the left column to go to symbol view of the module.
-unit are default as the following, more is available in .lib you copied from bsac account.
time_unit : "1ns" ;
voltage_unit : "1V" ;
current_unit : "1uA" ;
pulling_resistance_unit : "1kohm" ;
capacitive_load_unit(1, pf) ;
-if you want to specify multiple pins with the same attribute, for example, a few pins with same load, use shift-click to select multiple pins, choose attribute->
operating envi->load. Leave the name blank and assign values, and those values will go to all selected pins.
-When specifying timing constraints, I had problems using the Attributes menu, so I took the second approach.
setup->command window, type the following script, press “Enter” after each line:
set_max_delay 100 -from pin1-to pin2 (setting pin to pin max_delay)
set_max_delay 40 –from clk1 -to U9 (setting clock (clk1) to instance(U9) max_delay)
7. Map the verilog codes into a design based on standard library files you chose in 2. Do mapping and verification with Tools->Design Optimization.
-If you have a “1” at the end of your compile log file, it means mapping is successful.
-If you have a large design, it’s better that you map each individual module respectively, so that if you change certain module or change constraints to certain module, you only need to synthesis those modules and their related higher level ones, instead of re-synthesis the whole design, since mapping can be very time-costing for some design with tight constraints at high effort.
-After the mapping, inspect your design from top to bottom levels, all modules should be realized with standard cells by now.
8. Using file->Save As to export your file to whichever format you need.
9. Post-synthesis verilog simulation
-you might need to include following files:
no_delay_models.v
unit_delay_models.v
udps.v
These files can be found on bsac account. For example, if you chose std_digital library in 2, the directory would be:
/designPackages/cmos8/R4.0/release/libraries/std_cells/xlite_core_07/combined/verilog/
If you chose other library in 2, above files can be found under corresponding directory.