Projects
Smart Dust
(primary)
IrDA COTS Dust
in situ
Characterization of CMOS for Post-Process Micromachining (complete)
Monolithic Triaxial Accelerometer in Foundry CMOS
Characterization of CMOS Thin Film Mechanical Properties
µRTG
Microwave/millimeter wave MEM Devices (HRL)
Tools
Out-sourced Assembly and Packaging
Cadence
BSAC Cadence help
Plotting
, particularly large chips
Schematic Entry (Composer) Help
Simulation/Netlisting (Analog Artist) Help
Importing spice netlists into Cadence
Including text subcircuits and macros in Analog Artist
Verilog-XL and switch-level simulations Help
Verilog Tips
Using SimVision GUI for NCSim
Running Design Analyzer (front end for DC) at the BWRC
Avoiding assign statements in Design Compiler
VerilogIn
-- importing gate-level verilog netlist into Cadence
Running Synopsys Epic Nanosim (fast spice)
Creating a standard cell library for SE
Installing Hspice for Windows
Orcad
Tips from Jan and Bo
Usage tips
Lincoln Labs 0.25µm SOI process
technology files
Brett Warneke
-
last edited April 30, 2004
