when use VerilogIn to streamin the codes generated by synopsys, will meet
following problems:
1. synopsys have "assign" lines, which will cause problem in VerilogIn, NSC
has script to remove them, but double check after the removal if the lines are 
still connected.
2. synopsys have back slash (\) before certain net, say, wires, and VerilogIn
does not like that, once again, NSC has script to change that.
3. there two set of verilog models, under following directories:

/designPackages/cmos8/R4.0/release/libraries/std_cells/xlite_core_07/co
mbined/verilog_pg

/designPackages/cmos8/R4.0/release/libraries/std_cells/xlite_core_07/co
mbined/verilog

make sure to use verilog/files for synopsys, otherwise synthesis will have
problems.  this is the verilog models withOUT VDD or VSS.

4. after getting the gate implementation from synopsys, NSC has script to add 
VDD and VSS pins to the codes.  streamin those codes with VDD and VSS.

5.make sure to use ...verilog_pg/unit_delay_models.v in the -v option of 
VerilogIn form, this is the verilog models with VDD and VSS.

6. make sure xlite_core is listed in reference libraries.

7. due to unknow reason, if you put VDD in the Power Net Name of verilogIn
form, there will be some error.  instead, put myvdd there.  for the gnd pin, 
it does not have the problem, you can just use VSS.