Fall 2010 IAB
September 15 to 17
Integrated Circuit Design with Nano-Electro-Mechanical Relays
No matter how slowly they are allowed to run, digital logic gates implemented with CMOS transistors have a well-defined minimum energy that they must dissipate for each operation they perform. This minimum energy dissipation in CMOS can be traced back to the imperfection of transistors as switches - in particular, that their sub-threshold swing is limited to be no steeper than 60mV/decade at room temperature.
In contrast, switches based on mechanically making or breaking physical contact can achieve zero leakage and nearly infinite sub-threshold slope, and hence may someday enable drastic reductions in energy. However, realizing this goal requires substantial innovations to improve the performance and reliability of the devices themselves, as well as to develop circuit and system design techniques tailored for these devices.
Therefore, in this talk I will begin by showing that insights into optimized relay-based digital circuit design allow one to substantially mitigate their perceived disadvantages such as poor reliability, relatively large switching delay, and device layout area. In addition to highlighting the potential energy savings of a scaled relay technology, I will conclude the talk by presenting measured results from an initial test-chip demonstrating the functionality of multiple relay-based integrated circuits.