Using Ambit Build Gates

by Jason Hill

This tutorial is a walkthrough of how I used Ambit Build gates... I am not claiming to be an expert or even an EE student.

Simulate your VHDL...

• I used LDV  run make to see it compile, run make sim to pop up the simulation environment.
• Note that you have to use the cds.lib.vhd to run the simulator and compiler under NT.

Compile your code:

• First get a copy of xlite_core.alf  which was generated using libconvert on the synopsis libraries. You have to have signed the National NDA.  If not you can use a default "lca300k.alf" file instead.
• Put all your VHDL files into a new directory with the alf file.
• Run ac_shell (ac_shell -gui works too)
• I find ac_shell at /usr/eesww/cadence/02/SPR4.0/BuildGates/V4.0-s008/bin/ac_shell
• Enter the following set of commands to get your netlist.  You have to read in your VHDL from bottom to top so that all modules are defined before they are used.  

>read_alf xlite_core.alf
>set_global hdl_vhdl_environment common  (this controls which ieee.std libraries are included)
>read_vhdl my_vhdl1.vhd  (read_verilog works too)
>read_vhdl my_vhdl2.vhd
>do_build_generic  (this will do the synthesis)
>do_optimize  (this will map the synthesized logic to xlite_core cells provided by national)
>write_verilog -hierarchical my_netlist.v)

• Finally, you need to slightly modify your netlist to include connections for VDD and VSS into every node.
• To to this I use vi.  I open up the file and run the substitiution: :%s/);/, .VDD(VCC), .VSS(VSS));/
• Unfortunately, you have to go and fix up each of the module definitions so that they only have the net name in their declarations and not the assignment.  You also have to list the VCC and VSS as inputs and supply0 and supply1 as appropriate.

Import your code. -- follow Seth's tutorial code from here...