Cadence Design System
Notes on Using Composer and Analog Artist
Introduction
General
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to set the default unit scale (such as mm instead
of meters) go to Tools®CDF®Scale
Factors... in the CIW. In the default auto mode, sub-micron
gate lengths will be specified in nanometers with significant digits extending
into the sub-angstrom regime.
Schematic Entry (Composer)
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Openbook Tutorial: IC Tools®Tutorials
and Flow Guides®Composer
Tutorial
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Openbook Documentation: IC Tools®Schematic
Entry®Composer:
Design Entry Help
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use Design®Create
Cellview®From
Cellview command to generate a symbol from a schematic,
or vice versa.
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parameterized components: use pPar("CDF_parameter_name")
in the properties form for the parameter. For example, parameterize
the gate width with W=pPar("wp").When
Create
Cellview-From Cellviewis used, the symbol will contain this parameter,
which can be adjusted in the the parent cell. If the cell is used
as a top level cell, the parameter can be specified by adding a user property
to the Edit®Properties®Cellview...
dialog
box to give the parameter a value.
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dependent parameterized components: use iPar("CDF_parameter_name")to
inherit parameters from the instance itself. For example, to make
the AD of a MOSFET a function of the channel width, defineAD=iPar("w")*5u
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Passing design variables from Analog Artist to components in Composer
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in Composer, use a string for the parameter that you wish to vary.
For example, specify the width of a transistor to be "wp".
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in Analog Artist, go to Variables®Edit...
and
enter each variable and its value. You can also use Variables®Copy
from Cellview to copy any unlisted variable in the schematic to
the Design Variable pane.
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look under the Analog Artist section to see how to sweep variables (Parametric
Analysis)
Simulation/Netlisting (Analog Artist)
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Openbook Documentation: IC Design®Analog
and Mixed-Signal Simulation®Analog
Artist Simulation Help, Analog Artist Parametric Analysis Help, Component
Description Format (CDF) User Guide
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Setup®Simulator/Directory/Host
-- be sure to specify the full path for your project; specify what simulator
to use here (e.g. hspiceS).
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the Save State command doesn't seem
to save the path for the project and always defaults to ~/artist.
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Model File options:
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Cadence-style (allows parameterized models, facilitates corners, etc.)
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put each model in its own file (e.g. one file for PMOS, one for NMOS)
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name the file nnnnnn.m where nnnnnn is the model name (case
sensitive) used by the components in your schematic
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inside the file, each line that continues must end with an '&', instead
of a '+' on the beginning of the next line; this is Cadence Spice style
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remove all extraneous spaces from the model, including around '=' symbols
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parameters are passed through '&n' where n is the parameter
number. &1 is the model name, so the first two lines of the model
might be
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.model &1 NMOS &
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LEVEL=49 TOX=5.50e-09 &
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put the entire path to the directory containing these files in the
Setup®Model
Path... dialog box. Note that you can specify various
simulation corners (such as normal, fast, slow, etc.), and then put the
models for each corner in a separate directory.
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create an include file that has an .include statement for your model; you
can leave your model in standard Spice format
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Parametric Analysis (sweeping design variables)
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create design variables as described above under Composer
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Tools®Parametric
Analysis... to set up the analysis
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Temperature sweeps: In the variables window define a variable tempdc.
Cadence will recognize this variable as temperature and it can then be
used in parametric analysis.
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Stimulus Editor
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put input pins in the schematic wherever you want to put stimulus sources
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graphical editor: I always got the following error message: "Could
not find source, vdc, in refLibs," which prevents the editor from
figuring out how to configure the the dialog box for each type of source.
I tried setting up a refLib and searched the documentation, but couldn't
figure out how to fix this problem.
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text editor:
LVS
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In schematic, use Check and Save to
extract the schematic before running LVS.
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In Virtuoso, place pins on nets that leave the cell. These are correlated
with the pins in your schematic.
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