Cadence Design System

Using Verilog-XL, with particular application to the NSC CMOS8 Design Package

• Create a schematic in Composer using the symbol views from the xliteMS-core library; for some unknown reason, the xlite_core library does not put port names on the instantiation line when the schematic is netlisted.
• Tools®Simulation®Verilog-XL from Composer to start the Verilog-XL Integration Control or launch it from the CIW.
• Openbook help
• IC Tools®Digital Simulation®Verilog-XL Integration for Composer User Guide
• HDL Tools®Digital Simulation®Verilog-XL®Verilog-XL Tutorial
• IC Tools®Digital Simulation®Verilog-XL Integration for Composer Reference
• HDL Tools®Digital Simulation®Verilog-XL®Verilog-XL User Guide
• HDL Tools®Digital Simulation®Verilog-XL®Verilog-XL Reference
• Setup®Simulation...
• Other Options - add +define+no_delayed to have sequential logic circuits work
• Library Files -
• Verilog HDL for standard cells: /designPackages/cmos8/R3.0/release/libraries/mixed_signal/xliteMS_core_04/combined/verilog_pg/unit_delay_models.v
• UDPs (user-defined procedures) for sequential logic cells: /designPackages/cmos8/R3.0/release/libraries/mixed_signal/xliteMS_core_04/combined/verilog_pg/udps.v
• Delay Mode
• Unit seems to have no delay on edge-triggered DFF
• Path has a one unit delay on a singe edge-triggered DFF
• Setup®Netlist...  if Generate Test Fixture Template is not selected, the simulation seems to have trouble running.  Use Incremental netlisting to help preserve the Stimulus Template.
• Stimulus®Verilog... - add stimulus here to be put in the simulation automatically.  Unfortunately, this file often gets written over when netlisting, so should probably copy the default testfixture and make changes in the copy.
• Simulation®Start Interactive - netlists the design, generates the default test fixture, and starts the simulator
• select nodes in Composer (Shift to extend selection) to have them automatically inserted into the Monitor and Set Break forms, although this inserts the full path for the node, which can be a mess when Monitor lists the names
• Info®Monitor - list node names to be displayed whenever they change or at breakpoints
• Set Break button - add breakpoints on transistions or at a specific time; check with Debug®Utilities®Breaktool...
• Continue button to run simulation until the next breakpoint.  If there are no breakpoints, the simulation can run fast and take a while to shut down with Interrupt or Finish Interactive.  If there are no more transistions, the simulation will finish.  Specify signal changes by typing something like "#50 D = 1;"  The #50 specifies the number of time units relative to the current time step.  In a stimulus file, this would be relative to the previous line of the block.
• Debug®Utilities®View Waveforms... use to launch the SimWave viewer
• Hierarchy Browser... - can be used for setting the scope and focus
• after finishing a simulation, you must close both the VIC and the Composer windows before starting a new simulation
• Composer schematics use BUSname<0:7> format for busses, while Verilog-XL uses BUSname[0:7] format.
• To create a verilog view of a cell

Switch-Level Simulations with Verilog-XL

• need Verilog view on nmos and pmos cellviews
• to select nodes to watch, use the hiearchy viewer (tree symbol)

// Verilog stimulus file.
// Please do not create a module in this file.


// Default verilog stimulus. 
//reg In;
always
   begin
      #100 In=1;
      #100 In=0;
   end
   
initial
begin 

//   In = 1'b0;
   repeat (10) @In;
   $finish;
end

• could not get sequential logic cells to initialize the storage node, even when directly forced the node in Verilog-XL Integration Control; it would always remain an 'x'