Cadence Design System

Running Mixed-Mode Simulations, with particular application to the NSC CMOS8 Design Package

Design Setup:

• Create a schematic in Composer in the standard way.
• Brett recommends using NSC's xliteMS_core (mixed-signal) library rather than the xlite_core library since for some reason the xlite_core library does not put port names on the instantiation line when the schematic is netlisted.  (See Brett's page on  Verilog Help.)  This is indeed true, and while I have not found an elegant fix for this, there is a workaround that is described below.
• If you want to use cells from the xlite_core library to avoid getting the extra substrate pin for every cell, you will need to modify each xlite_core cell that you are using
• First copy each cell from the xlite_core library into one of your own local directories
• Select the cell from the xlite_core libary and deselect any of the views
• Library Manager®Edit®Copy
• Make sure that Copy All Views is selected and Copy Heirarchical and Update Instances are deslected
• Give it the new libary and cell name
• Go to the newly copied cell and open the verilog view
• Open the Cellview Property Editor in the Composer window using Edit®Properties
• Select the portOrder parameter and Delete it (don't just delete the text in the portOrder box, delete the entire property using the Delete button in the dialog box)
• Click OK and then save the verilog view
• Now you can use these new local xlite_core cells with the modified verilog view in your design and the netlist will come out correct...not pretty, but it works
• Use only input or output pins in your schematic, NOT pins of type in-out where you will need Interface Elements (on the boundaries between analog/digital blocks, such as Vdd, Gnd and inputs/outputs of logic gates).  Otherwise, Cadence is not able to determine the type of Interface Elements to place in the design.

Partitioning the Design:

• Partitioning your design is the process of specifying the type of simulator that should be used for each cell in your design hierarchy
• This is done through the Cadence Hierarchy Editor, which makes a new cellview called the config view
• Go to the Library Manager and create a new cellview for the cell you want to simulate using File®New®Cellview
• Specify config as the View Name and Hierarchy-Editor as the Tool and hit OK
• This brings up two dialog boxes, the New Hierarchy dialog and the Hierarchy Editor dialog.
• In the New Hierarchy dialog, choose a Template from the Built-In list that best describes the simulator that you will be using.  This automatically fills in a lot of default information in the View List and Stop List that is basically correct for that particular simulator.
• For Top Cell, specify the appropriate Library, Cell and View (View should be schematic)
• In the Global Bindings section, you need to specify the View List and the Stop List
• The View List is a list of cell views that the simulator will use to descend into your design hierarchy.  The default entry is $default, and as such it is unclear what views are contained in that default list.  Therefore, I always specify my View List directly as described below.
• The order of the views is important, as the simulator searches for each view type in the order specified.  Thus, you should specify the view names in the order in which you would prefer the search to be performed.  (eg for a simulator of spectreSverilog, a typical View List would be:  verilog spectreS schematic, indicating that you prefer the verilog view if it exists, etc.)
• The Stop List is a list of cell views which are termination views for the simulator.  Thus, these are views which are possible to directly simulate.
• Once again, the order of the views determines the search priority for the simulator.  (eg for a simulator of spectreSverilog, a typical Stop List would be:  verilog spectreS, indicating that you prefer the simulator to simulate the cell using Verilog-XL rather than spectreS if a verilog view exists)
• Click OK in the New Hierarchy dialog to complete the initial partitioning setup.
• The Hierarchy Editor dialog remains on the screen, and it is in this dialog that you can specify even more detailed control over the simulation partitioning.
• Under the Cell Bindings section is a list of all of the cells in your design, along with some information regarding the simulation views that will be used for that cell.
• At this point, it is possible to specify directly which view will be used for each individual cell if you prefer a different view than the default view (listed as the View Found column).  This may be a good idea if there is a digital block in your design that you would prefer to simulate in the analog domain for some reason.
• To override the default View Found for a cell, simply type in a new view name (eg spectreS) in the View To Use column for that particular cell.
• When you are finished customizing the partitioning of your design in the Hierarchy Editor dialog box, save the config view by using File®Save
• Exit the Hierarchy Editor using File®Exit

Specifying the Interface Elements (IE):

• Interface Elements are used between analog and digital elements in the simulation.  Cadence inserts these automatically where needed in your design, but you must specify the logic levels and speed of the interface elements for things to work correctly.
• Open the newly created config view from the Library Manager.
• A dialog box will ask if you would like to open both the config view and the schematic view (the config view is sort of "attached" to the schematic view).  The default is to only open the schematic view, which works fine.
• Note that when the schematic opens in Composer, the title bar indicates that there is a config view associated with it.
• Enable the Mixed-Signal options by choosing Tools®Mixed Signal Opts.
• Choose Mixed-Signal®Interface Elements®Library...
• Make sure that IE Library Name is analogLib and that IE Model Name is MOS (actually there is a CMOS8_MOS element in the CMOS8 library that uses 0-2.5V as the logic levels, but since you may be using a different supply voltage, it is better to specify levels directly)
• Choose Output as the Model IO to modify the D/A elements
• Specify the desired fall time (d2a_tf), rise time (d2a_tr), high logic voltage level (d2a_vh), and low logic voltage level (d2a_vl)
• Click Apply
• Choose Input as the Model IO to modify the A/D elements
• Specify the desired low logic threshold (a2d_v0) and high logic threshold (a2d_v1).  These should be centered around your supply voltage divided by 2.  (eg for Vdd of 1V, V0=0.4 and V1=0.6 would work)
• The a2d_tx parameter sets the maximum time between valid threshold levels set above before an X is declared on the output. The default of 1 ms is probably fine for most purposes.
• Click Apply
• Click OK to exit out of the dialog box.
• Choose Mixed-Signal®Interface Elements®Default Options...
• Make sure that Default IE Library Name is analogLib and Default IE Model Name is MOS and Detailed IE Generation is unchecked
• At this point, you can also play around with some of the other Mixed-Signal menu items, allowing you to do such neato things as color code the analog, digital and mixed cells and other such games.  They are all pretty self-explanatory and don't seem to be critical to getting the simulation to work, so I'll spare you all the details.

Setting up the Simulation:

• At this point the schematic view and config view are ready for simulation.  Simulations are setup through the standard Analog Environment dialog box as before.
• Open Analog Environment from the schematic view by choosing Tools®Analog Environment
• Make sure that the Design parameters are correct, particularly that the View is config
• Setup the simulator that is to be used by choosing Setup®Simulator/Directory/Host...
• Specify a mixed-mode Simulator such as spectreSverilog or hspiceSverilog (the exact simulator depends on the view types and/or template that you specified in the Hierarchy Editor)
• Setup the Model Path using Setup®Model Path...
• The model path specified here is only for your analog models, so simply specify the normal path you use for your spectre or spice models for cmos8
• Setup the Environment Options using Setup®Environment...
• Set the Mixed Signal Netlist Mode to Hierarchical
• Hit the Verilog Netlist Option.... button to bring up the Verilog HNL Netlisting Options dialog
• Check the Generate Test Fixture Template button and specify Verimix as the Template
• Make sure the Drop Port Range option is checked
• Setup the analyses to be performed in the standard way, Analyses®Choose...
• Setup any Variables and Outputs in the standard way as well
• At this point, you must specify some options for the Digital Simulator
• Choose Simulation®Options®Digital...
• This brings up the Verilog-XL Simulation Options dialog box.  Specify the following options (everything not specified can be left at the default)
• Delay Mode
• Unit seems to have no delay on edge-triggered DFF
• Path has a one unit delay on a singe edge-triggered DFF
• Other Options - add +define+no_delayed to have sequential logic circuits work
• Library Files
• The following paths for the verilog library files assume that you are using gates from the xliteMS_core library.  Modify the paths arppropriately if you are using the xlite_core library.
• I have not found a way to get the simulator to use more than one library file at once.  Simply entering both files with a space between them in the dialog box does not work, nor does entering a comma between the files.  But there is a workaround if you are using both combinational and sequential logic cells that is described below.
• To use multiple verilog library files, simply concatenate the verilog files listed below together into a new file and use this new file as your library file.
• Example:  cat /designPackages/.../unit_delay_models.v /designPackages/.../udps.v > ~username/cmos8_verilog.v
• Then specify ~username/cmos8_verilog.v as the single library file that you are using.
• Verilog HDL for standard cells: /designPackages/cmos8/R4.0/release/libraries/mixed_signal/xliteMS_core_04/combined/verilog_pg/unit_delay_models.v
• UDPs (user-defined procedures) for sequential logic cells: /designPackages/cmos8/R4.0/release/libraries/mixed_signal/xliteMS_core_04/combined/verilog_pg/udps.v
• Verilog-XL Executable
• Specify /usr/eesww/cadence/02/LDV3.3/tools.sun4v/verilog/bin/verilog.vmx as the executable
• Click OK to finish specifying the Digital Simulator Options
• This is a good time to save your Analog Environment state, since everything should be set properly at this point.  Use Session®Save State... to save the simulation state.  Next time, you simply need to specify the design and simulator and then load this state using Session®Load State...

Running the Simulation:

• Run the simulation in the normal way, either Simulation®Run or click the Green stoplight button.
• Saved waveforms can be viewed in the normal way after simulation (eg using Calculator)