Setting up Silicon Ensemble - Tutorial Guide

by Seth Hollar and Mark Chew

Silicon Ensemble is an auto-place and route tool by Cadence. It is designed to place digital blocks quickly and efficiently. Below are instructions on how to integrate SE into the jupiter process flow. In addition to this tutorial guide, a hard copy SE manual is located on my desk. Feel free to drop by and borrow it. The instructions below were performed on the schematic view of j23_shollar/seq1. Files generated from this flow are located in ~shollar/SE/seqtest1 for tutorial files.

• Copy your verilog netlist file to your design-specific directory, and rename it netlist.v. Open "netlist.v" with a text editor, replace "cds_globals.gnd_" with "gnd" and "cds_globals.vdd_" with "vdd," and save. Query replace all work well in Emacs. Use the Control-Meta-% for query replace. "!" does all replaces without asking.
• Copy "dummy_models.v" and a "xlitecore4m.lef" to the same directory where you'll run SE. These are available at "~shollar/national/SE2icfb/SEfiles/". Xlitecore4m.lef was generated by SE's "Abstract Generator", a really buggy program that barely gives you what you want. Currently an LEF file is created for the xlite_core library. It is possible to create an LEF file for the mixed signal xlite core, though no documentation for it has been written up yet.
• Open Silicon Ensemble (by typing in "seultra" or "seultra -m=120") in your design-specific directory. File->import->LEF, to import the xlitecore4m.lef file you just copied. seultra -m=120 gives you more memory if you need it (120 Megabytes).
• Import "netlist.v" and "dummy_models.v" by going to file->import->verilog, making sure to mention the name of your top module where the form asks for "verilog top module." Be aware that the browsing command doesn't work for more than one file. You may have to add dummy descriptions to dummy_models.v if one or more of your modules isn't already in that file. Make sure to take off the "!" from the "options" part of the form where it asks for you to specify nets. The "!" indicates a global vdd or gnd, so remove these if you're just trying to lay out a local vdd and gnd, relative to your design.
• Unfortunately, the LEF file only supports stuff in the xlite_core library and not in the xliteMS-core library. This means that components in the initial schematic must be from the xlite_core library. There's currently a problem where the xlite_core components don't get their pins attached in the netlist, but that problem can be fixed by following these directions: How to get xlite_core components to netlist properly
• Floorplan-Initialize Floorplan. Use the help button for more information on what each parameter is. Select "Flip Every Other Row," which will put your vdd's and gnd's together. For I/O to core distance, you can put something around 18 um if you don't know what else to put. Row Utilization indicates how densely SE will pack each row - higher numbers give you more dense designs, but smaller numbers will make it run faster.
• Place-IOs. Probably OK to choose random placement, unless you have some special placement needs.
• Place-Cells. I just use the defaults and hit OK. It should now lay out your design for you.
• Place-Filler Cells-Add Cells. This fills out the space in your rows. The model is "FILL_TAX0" and you can give it whatever prefix you want, like "f1." Hit OK, and it should fill in the extra space for you.
• Route-Plan Power-Add Rings. Change the core ring width and block ring width to be a multiple of the your feature size, like 3.6 um. (For both horizontal and vertical.) Hit OK. This puts down your power rings.
• Route-Connect Ring. You generally won't have to change the default settings, so just hit OK. This should connect the power rings to your design.
• Route-WRoute. Make sure the "global and final route" option is selected. This may take some time to process.
• File-Export-GDS II. For the map file, copy a gds2.map file to the directory you're running SEultra in, and type in its name. ("gds2.map" if you don't change the name) This is available at ~shollar/SE. gds2.map is NOT a gds2 mapping file you normally use. It is SE specific. I spent many a hours trying to figure this out.
• In the main "icfb" window, File-Import-Stream. Where it asks for the "Template File," type in: ~shollar/national/SE2icfb/SEconvert. Template file: "SEconvert" Under "Input File," type in the name of the file you exported from Silicon Ensemble. Type in the name of the library you want to import to, under "Library Name." Click the "User-Defined Data" button. Under "Layer Map Table," type in "~shollar/national/SE2icfb/convertlayer.map." Under Options, click on "retain reference library". This is very important. In order to import in the cell references the path library must contain the xlite_core library. During the import process, icfb finds matching cells in the library path that go along with the referenced cells in the gds2 file. Beware, confusion may arise if you have two cells with the same name in two different libraries. Hit OK, and after it's done thinking, the new layout should appear in your library manager.
• Don't forget to attach the right technology file, if you created a new design library.

How to get xlite_core components to netlist properly

I used the schematic view from seq1 located in j23_shollar for this example.

Creating a netlist in verilog.

• Get a new version of the xlite_core components, by editing the library path in your library manager. Call the library xlite_SE and let the path be ~shollar/national/xlite_core. This is basically a writeable version of the xlite_core library. DO NOT change the cells in this library if you don't know what you're doing because this directory is writeable, and other people will be using your modified versions of the cells. (Only if you already drew up your schematic.) For all the symbols in your schematic, replace them with xlite_SE versions by clicking on the symbol, hitting "q" (for properties), and changing the library name.) For each of the symbols you use, go to your library manager, choose library xlite_SE, and the cell that matches your symbol. Open this cell with the verilog view. Edit-properties. Scroll down, looking for a line that says "portOrder." If you see such a line, left click in the corresponding box and hit the delete button at the top of the box, not on the keyboard. Close by going window-close, and repeat this for all the other symbols you're using.
• Open schematic -> tools -> simulation -> verilog XL
• Specify verilog directory
  Setup ->simulation -> more -> library files:
  ~shollar/national/SE2icfb/SEfiles/dummy_models.v
  
• run simulation, if it runs successfully, then the netlist has been created. If not, perhaps not all of the cells have been modified from the previous step.. To view netlist, go to the verilog directory and the subdirectories:ihnl/cds0/netlist